1. Field of the Invention
The present invention relates generally to a printed circuit board for use in a probe card for testing a semiconductor wafer, and more particularly, to a multilayer printed circuit board having clustered vias in power layers to facilitate the routing of signal traces in signal layers.
2. Description of Related Art
Probe cards are on, or typically include, printed circuit boards (“PCBs”) and are utilized to distribute signals, power, and ground between a remote host tester and a semiconductor device under test (“DUT”) resident on a wafer under test (“WUT”). Typically, thousands of signals are communicated between the remote host tester and the DUTs resident on a WUT. As a result, a signal routing scheme must be incorporated into the design of a probe card's PCB.
Referring to FIG. 1, a newly developed probe card 10 of the assignee of the present invention has a diameter “D” of 12 to 18 inches. Signals input along the outer region 12 of the probe card 10 are routed to an interior active region 14 having a 2.5 inch square area. Referring now to FIG. 2, the interior active region 14 includes an array 16 of conductive contact elements 18. A contact element 18 is ultimately connected through a probe tip (not shown) for contact with a pad of a device under test.
Although the array 16 of this new probe card includes thousands of contact elements 18, a seven by seven array is illustrated for clarity. Each horizontal row of contact elements 18 is separated from a neighboring row of contact elements by a horizontal channel 20. Each vertical column of contact elements 18 is separated by a neighboring column of contact elements 18 by a vertical channel 22. Each contact element 18 is connected to a trace 24 that may carry a signal, ground, or power from the outer region 12 of the probe card 10 to the contact element 18. The traces 24 are laid down using conventional PCB techniques such as, but not limited to, photo lithographic masking, etching and/or sputtering. As discussed in further detail below, in one embodiment, only one trace 24 can pass between any pair of neighboring contact elements 18 given the close dimension design of this new probe card. Accordingly, a drawback encountered in routing is the difficulty in laying down traces 24 that connect all the contact elements 18 in an array to their corresponding signal, power, or ground sources located at the outer region 12 of the probe card 10. For example, when contact element 18c is connected to a ground source via ground trace 24c and contact element 18d is connected to a power source via power trace 24d, contact elements 18a and 18b cannot be connected to signal sources because the adjacent horizontal and vertical channels 20 and 22 are occupied by the ground and power traces 24c and 24d due to the close spacing required between the contact elements 18 in this new probe card.
A multilayer PCB overcomes, to some extent, the above-described drawback. Turning now to FIGS. 3 and 4, a portion of a multilayer PCB 26 of the new probe card includes one or more power layers 28, signal layers 30, and ground layers 32. Although the multilayer PCB can include dozens of layers, a seven layer PCB portion is illustrated for clarity. Each ground layer 32 controls the impedance of one or more adjacent signal layers 30 and can also provide signal isolation between neighboring signal layers 30. The ground layer 32 may also provide ground to selected conductive vias 34. The vias 34 are shown in FIG. 3 before they are filled with metal. A ground layer 32 may be a polymeric dielectric or ceramic dielectric layer, which is metal clad 62 on a side not in contact with the signal traces on adjacent layers. Generally, a ground layer 32 is situated between the opposing planar surfaces of two neighboring signal layers 30. While the figures depict a ground layer 32 between each pair of signal layers 30, this is generally not necessary and a ground layer 32 need only be interspersed between some of the signal layers 30, depending on the circuit design considerations of signal isolation.
The signal layers 30 contain signal traces 24 which route signals from the outer region 12 of the multilayer PCB 26 to selected conductive vias 34. The power layers 28 may contain power traces 25 which route voltages (e.g., Vdd and Vss, which can be on different power layers in the new probe card design) from the outer region of the multilayer PCB 26 to selected conductive vias 34. Alternatively, large energized planar regions of the power layers 28 can be energized by different voltage sources (e.g., either all Vdd or all Vss, or combinations of both) and selected conductive vias 34 can be electrically connected to the energized regions while the remaining conductive vias 34 are kept electrically isolated from the energized regions of the power layers 28. It should be noted that where “power” is referred to herein, any and all power connections are included. Recent trends in technology have tended to push the decision of semiconductor devices in the direction of single voltage supplies, and this terminology reflects this trend. However, herein, the term power refers to all required power supply voltages.
Electrical connections 36 electrically connect contact points on the signal traces 24, power traces 25, or energized planar regions 54 (see FIG. 8) of the power layers 28 to the conductive vias 34 which, in turn, are electrically connected to the contact elements 18 mounted on the lower surface of the multilayer PCB 26. In some of the figures these connections between the vias and the traces 24, 25, or regions 54 are diagrammatically shown as slash (“\,”) marks. It is to be understood, however, that the actual electrical connections 36 may be formed using conventional techniques such as photo lithographic masking, etching and/or sputtering to cause the traces 24, 25 and regions 54 to be formed up to the edges of the selected metal filled vias 34 to electrically connect to them. See, for example, FIGS. 8 and 9.
By this arrangement, the routing drawback encountered by single layer PCBs is overcome since multiple signal, power, and ground layers are provided for routing signal, power, and ground traces such that all the contact elements 18 in the active region 14 of a PCB 12 are connected to their corresponding signal, power, or ground sources located at the outer region of the PCB 12. For example, as shown in FIG. 4, contact elements 18c and 18d can be electrically connected to power traces or power regions located on the power layers 28 without impeding contact elements 18a and 18b from being electrically connected to signal traces provided on the signal layers 30.
While multilayer PCBs facilitate the routing of signals, power, and ground between a remote host tester and a DUT, these PCBs have a number of drawbacks.
Referring now to FIGS. 5(A) and 5(B), a multilayer PCB manufacturing method can include masking circuit or trace patterns onto the individual power layers 28, signal layers 30, and ground layers 32. Afterwards, an adhesive is applied to the layers 28, 30, and 32, and the layers 28, 30, and 32 are aligned and combined to form a vertical stack 38. Vias 34 are then drilled through the vertical stack 38. Next, the vias 34, 34a and 34b are seeded or plated to create vertical conductive pathways between selected traces or regions (see FIG. 3) and the contact elements (see FIG. 4) which are later mounted over the via openings at the lower surface of the vertical stack 38.
Turning now to FIG. 6, a representative signal layer 30 generated by the above-described manufacturing method is shown. Vias 34a represent vias that interconnect the power layers 28 (located below the signal layers 30) to the contact elements 18 on the lower surface of the multilayer PCB. Vias 34b represent vias that interconnect the signal layers 30 or ground layers 32 to the contact elements 18 on the lower surface of the multilayer PCB 26. In the multilayer PCBs of the assignee's new probe card, vias 34a and 34b have 24 mil diameters and are spaced apart on 50 mil centers. An additional 5 mil space extending around the outer region of the vias 34a and 34b is kept free of trace circuitry 24. This 5 mil space allows for machining and human errors in positioning the vias 34a and 34b such that a signal trace 24 will not be clipped during a via forming process, such as drilling, if vias 34a and/or 34b are slightly misaligned. Therefore, a via's “footprint” in this design is approximately 34 mil. The signal traces 24 in this design, preferably, have 7 mil widths and 14 mil spacing.
There are a number of disadvantages in manufacturing a PCB of this design using the conventional method steps just described. First, only one signal trace 24 can pass between any pair of neighboring vias 34a and 34b since the channel between a pair of neighboring vias 34a and 34b is 16 mil. Therefore, the presence of the vias 34a reduces the number of signal traces 24 that can be laid down on a given signal layer since only one signal trace 24 can pass between a pair of neighboring vias 34a and 34b. Accordingly, a multilayer PCB manufacturing step of drilling vias through all the layers of the PCB, regardless of what conductive pathway is established by a given via, would result in inefficient routing of signal traces on the signal layers of the PCB since signal layer real estate is squandered on vias (e.g., vias 34a) that only establish electrical pathways below the signal layers.
Second, additional signal layers must be incorporated into a conventional multilayer PCB to permit routing of signal traces since the presence of vias in all the signal layers limits the number of signal traces that can be laid down on each signal layer. As can readily be appreciated, the incorporation of additional signal layers increases the size of the PCB which, in turn, increases the size and cost of a probe card utilizing the PCB.
Third, vias can only be drilled through a limited number of ground, signal, and power layers. The limiting parameters are the via diameter and the drill capability, i.e. for a given length of hole, there is a practical lower limit for the diameter of the drill. As a result, only a finite number of signal layers can be incorporated into a probe card's PCB. Therefore, there is a limit to the number of additional signal layers that can be used to route signal traces around voltage vias. As can readily be appreciated, an upper limit of signal layers is quickly reached as the complexity of the PCB routing scheme increases.